1. Field of the Invention
This invention relates generally to the packaging of semiconductor dice and, more particularly, to the packaging of semiconductor dice to facilitate vertical mounting on a printed circuit board.
2. Description of the Related Art
Semiconductor dice are normally formed in large quantities on a wafer of semiconductor material, for example, silicon. After the dice are singulated from the wafer, they may be individually packaged in a plastic or ceramic package, for example. A lead frame may support the die for wire bonding and packaging and provide the lead system for the completed package. In general, electrical circuitry formed on the die is coupled to bond pads on the die to facilitate interconnection of the electrical circuitry with the outside world. During the wire bonding and packaging process, each bond pad is electrically connected by way of wire leads to the lead frame. The electrical connection includes a wire bond formed on the bond pad, a wire lead and a wire bond formed on the lead frame. An encapsulating material protects and insulates the die, and the die is mounted in a package having external pins for interconnecting the electrical circuitry on the die, via the wire bonds, to the outside world.
The packaged die may be mounted to a printed circuit board for constructing an electronic-device such as a computer. One problem associated with conventionally packaged die is that the package occupies a relatively large amount of space on the printed circuit board. To address this problem, multi-chip modules have been developed that utilize bare or unpackaged semiconductor dice. However, because bare dice are thin and fragile, packages called connectors have been developed to electrically connect and house multiple bare dice for mounting a supporting substrate to a printed circuit board. One problem with this type of connector is that it is difficult to make a reliable electrical connection to a bare die. In addition, the bare die is often damaged during insertion into the connector.
Another method that has been developed to address the above-mentioned problem associated with conventionally packaged dice involves the addition of contact pads to the integrated circuit device. The contact pads are aligned along one edge of the die, and each contact pad is interconnected by means of an electrical trace to a bond pad on the die. Thus, each of the bond pads on the die is electrically coupled to a contact pad, all the contact pads being situated along a single edge of the die. After an encapsulating material is deposited or otherwise formed over the die, openings are made in the encapsulating material over the contact pads. A multi-chip holder, having electrical contacts on its bottom surface, is adapted to receive multiple dice oriented vertically in the holder. The contacts at the bottom surface of the holder engage the contact pads on the edge of the encapsulated die and mate with electrical traces on a printed circuit board to complete the interconnection between the electrical traces on the printed circuit board and the electrical circuit on the encapsulated die. This method is illustrated in U.S. Pat. No. 5,593,927 to Farnworth et al., entitled xe2x80x9cMETHOD FOR PACKAGING SEMICONDUCTOR DICExe2x80x9d. Although encapsulation provides additional protection to the die, this method nevertheless suffers from some of the same deficiencies of previous methods.
The present invention includes a method for packaging a semiconductor device comprising connecting a plurality of wire leads to a corresponding plurality of electrical connection pads on the semiconductor device. The method further includes covering at least a portion of the semiconductor device and at least a portion of each of the wire leads with an encapsulating material. Finally, the method includes removing a portion of the encapsulating material and a portion of each of the wire leads to form a packaged semiconductor device wherein each of the wire leads has an exposed portion at a surface of the encapsulating material.
The present invention also includes a packaged semiconductor device comprising an integrated circuit device having a plurality of electrical connection pads and a plurality of wire leads coupled to the plurality of electrical connection pads. The device includes a covering of encapsulating material covering at least a portion of the integrated circuit device and covering each of the wire leads, wherein each of the wire leads has an exposed end.
The present invention further includes a processed semiconductor wafer comprising a semiconductor wafer having first and second integrated circuit devices formed on a first surface of the wafer. A plurality of wire leads is coupled between the first and second integrated circuit devices, and a covering of encapsulating material covers at least the first and second integrated circuit devices and the wire leads coupled between the first and second integrated circuit devices.